Analysis of Power Amplifier Modeling Schemes for Crosscorrelation Predistorters

Amplification of signals with fluctuating envelopes leads to distortion because of non-linear behavior of the Power Amplifier (PA). Digital Predistortion can counteract these non-linear effects. A crosscorrelation predistorter is a digital predistorter, based on the calculation of crosscorrelation functions using coarsely quantized signals. The crosscorrelation functions are transformed to the frequency domain and the spectra are used to calculate the coefficients of the predistorter memory polynomial. This method has reduced complexity and equivalent performance in comparison with existing schemes. In this paper, four alternative schemes to implement a crosscorrelation predistorter are analyzed. The PA characteristics can be determined either directly or indirectly using ’normal’ or orthogonal polynomials giving four alternatives. All four alternatives give significant reduction of Adjacent Channel Interference

Feedback Quantization in Crosscorrelation Predistorters

Amplification of signals with fluctuating envelopes inevitably leads to distortion because of nonlinear behavior of the power amplifier (PA). Digital predistortion can counteract these nonlinear effects. In this letter, the crosscorrelation predistorter is described and the effects of quantization in the feedback path are presented. One of the effects is that the quantization noise is correlated with the signal to be quantized, resulting in reduced performance of predistortion. A technique to reduce these effects is to inject a dither signal before quantization. Because of the quantization noise and dither signal, more data has to be used to obtain estimates of the PA behavior that are accurate enough for effective predistortion

A crosscorrelation predistorter using memory polynomials

Amplification of signals with fluctuating envelopes inevitably leads to distortion because of nonlinear behavior of the power amplifier (PA). Digital predistortion can counteract these nonlinear effects. In this paper, a digital predistortion architecture is presented which is based on the calculation of correlation functions using coarsely quantized signals. The crosscorrelation functions are transformed to the frequency domain and the spectra are used to calculate the coefficients of the predistorter memory polynomial. This method has reduced complexity and slightly improved average performance in comparison with existing schemes

Modeling Power Amplifiers using Memory Polynomials

In this paper we present measured in- and output data of a power amplifier (PA). We compare this data with an AM-AM and AM-PM model. We conclude that a more sophisticated PA model is needed to cope with severe memory effects. We suggest to use memory polynomials and introduce two approaches to deduce the polynomial coefficients from the measured data: the Least-Squares and Crosscorrelation approaches. We construct PA models according to both approaches, using the measured data. We compare the two PA models with the original AM-AM and AM-PM model

Frequency Offset Tolerant Demodulation for Low Data Rate and Narrowband Wireless Sensor Node

The issue of frequency offset in low data rate, narrowband and low power communication nodes is considered in this paper. To avoid power hungry precise frequency generation, offset tolerant demodulation and detection schemes are investigated. A Short-Time DFT (ST-DFT) based detection for BFSK is introduced which improves the BER performance of an existing design by almost 1dB. Its BER performance and complexity are also compared to frequency offset tolerant DDBPSK demodulation. Additionally, the effect of wider filter required to capture signal in presence of frequency offset is considered. The trade-off between performance and complexity for different offset values and filter bandwidths is discussed. Both methods work independent of frequency offset; however, it is shown that wider filters do not affect ST-DFT BER performance in contrast with DDBPSK. This robustness is obtained at the expense of increased computational load

Low-Complexity Hyperspectral Image Compression on a Multi-tiled Architecture

The increasing amount of data produced in satellites poses a downlink communication problem due to the limited data rate of the downlink. This bottleneck is solved by introducing more and more processing power on-board to compress data to a satisfiable rate. Currently, this processing power is often provided by custom off the shelf hardware which is needed to run the complex image compression standards. The increase in required processing power often increases the energy required to power the hardware. This in turn pushes algorithm developers to develop lower complexity algorithms which are able to compress the data for the least amount of processing per data element. On the other hand hardware developers are pushed to develop flexible hardware which can be used on multiple missions to cut development cost and can be re-used for different missions. This paper introduces an algorithm which has been developed\ud to compress hyperspectral images at low complexity and describes its mapping to a new hardware platform which has been developed to offer flexibility as well as high performance processing power called the Xentium tile processor